Microstrip Impedance Calculator

Controlled-impedance PCB work starts with a physical promise: a copper route and its return plane must present a predictable ratio of voltage to current as a signal wave travels along the board. That promise matters for RF feeds, high-speed serial links, video lines, clock routes, antennas, and any net where reflections or timing error can turn a tidy schematic into a noisy product.

Microstrip is the outer-layer version of that transmission-line problem. The signal trace sits on the board surface, the reference plane sits below it, and the electric field spreads through both laminate and air. Because the field is split, a microstrip is described with an effective dielectric constant, Eeff, rather than the laminate dielectric constant alone.

Z0

Characteristic impedance, reported in ohms, for the chosen cross section.

Dk

Relative permittivity of the laminate material between trace and plane.

W/H

Trace width divided by dielectric height, the main geometry ratio in closed-form microstrip equations.

Finished copper

The manufactured trace width and thickness after etching and plating, not just the CAD drawing value.

The most useful first estimates come from four stackup facts: finished trace width, height to the reference plane, finished copper thickness, and laminate Dk. Wider traces usually lower impedance because they couple more strongly to the plane. More dielectric height usually raises impedance. Higher Dk lowers impedance and slows propagation. Copper thickness becomes more important on thin dielectrics, where the trace sidewalls are no longer a tiny part of the geometry.

Manufacturing details make the estimate more than a geometry exercise. A board house may compensate artwork width for etch, plate the outer copper beyond the base foil, quote a laminate Dk at a specific frequency, or measure coupons under a defined time-domain reflectometry setup. Generic FR-4 values and nominal copper weights are useful for early planning, but they are weak evidence for a production controlled-impedance note.

Closed-form microstrip equations are best used to size a starting trace, compare model sensitivity, and see how tolerances move the result. Final sign-off still belongs with the fabricator's stackup model, a field solver when needed, and measured coupons for tight or high-risk nets.

How to Use This Tool:

Start with the stackup you actually intend to build, then choose whether you already know the finished trace width or need a width for a target impedance.

1. Choose Known width when you want the characteristic impedance for an existing trace, or choose Target Z0 when you want the trace width that reaches a requested single-ended impedance.
2. Select Equation model. IPC-2141 surface microstrip is the default and uses copper thickness in the impedance equation. Hammerstad-Jensen reference gives the zero-thickness comparison row.
3. Pick a Substrate preset or Custom Dk, then check Dielectric constant. Presets are starting values only; use the laminate value from the board stackup or material data when the route is impedance critical.
4. Enter Dielectric height as the spacing from the outer trace to the solid reference plane below it. Use the layer-pair spacing, not total board thickness.
5. Enter Trace width in known-width mode, or enter Target impedance in target mode. Target mode accepts 5 to 200 ohm and reports the solved width in the summary and Stackup Metrics.
   If the solved width is the main deliverable, compare the solved value in both millimeters and mils before sending a stackup note.
6. Set Copper thickness from finished copper when available, then open Advanced for Width tolerance, Line length, Reference frequency, Sweep span, and Display precision only when those details change the decision.
7. Review Stackup Metrics for the nominal value, Fabrication Window for W/H, T/H, tolerance, and mask cautions, and Trace Width Sweep for how quickly impedance changes around the current width.
   A message about Dk outside 1 to 20, a zero or negative dimension, target impedance outside 5 to 200 ohm, or an unsolved target means the result is not ready to use.

Interpreting Results:

The summary result is a nominal closed-form estimate from the selected model. In known-width mode, the main value is the calculated characteristic impedance. In target mode, the main value is the finished trace width that makes the selected model land on the requested Z0.

A near-target number is useful only after the stackup facts have been checked. Confirm the Dk source, height to the reference plane, finished copper width, solder-mask assumption, reference plane continuity, and expected trace-width tolerance before placing the value in fabrication notes.

A large IPC-2141 versus Hammerstad-Jensen spread does not prove either model is wrong. It signals that the geometry, copper-thickness assumption, or model choice deserves fabricator review or field-solver confirmation.

Technical Details:

A microstrip line is an inhomogeneous transmission line because part of the electromagnetic field travels in air and part travels in dielectric material. Closed-form equations replace that field distribution with an effective dielectric constant, then estimate characteristic impedance from the normalized trace geometry.

These quasi-static equations are fast enough for layout iteration and stackup discussion. They do not model loss, dispersion, copper roughness, trapezoidal etch shape, solder-mask loading, nearby copper, vias, launches, bends, or differential coupling.

Formula Core:

The IPC-2141 surface microstrip equation relates impedance to dielectric constant, dielectric height, finished trace width, and copper thickness. Height, width, and copper thickness must be converted to the same length unit before the equation is evaluated.

In that equation, Z0 is characteristic impedance in ohms, Dk is relative permittivity, H is dielectric height to the reference plane, W is finished trace width, and T is copper thickness. Increasing W or T makes the denominator larger and usually lowers impedance. Increasing H makes the logarithm larger and raises impedance.

For the IPC-style effective dielectric estimate, the width-to-height ratio controls how much of the field is treated as being in laminate rather than air.

The Hammerstad-Jensen comparison uses normalized width u = W/H, estimates Eeff with geometry correction terms, and divides an air-line impedance by the square root of Eeff. The shown Hammerstad-Jensen comparison is a zero-thickness reference, so it can differ noticeably from IPC-2141 when copper thickness is large compared with dielectric height.

Target-width solving searches for the width that makes the selected equation match the requested Z0. The search is monotonic for normal microstrip geometry because wider trace widths reduce impedance. If the requested impedance is above or below what the search range can reach, the target is reported as outside the solvable range for that stackup and model.

Delay uses Eeff to estimate velocity factor. A larger Eeff slows propagation because the wave behaves as if it were traveling through more dielectric material.

With Dk 4.3, H 0.18 mm, W 0.30 mm, and 35 um copper, the IPC-2141 result is about 49.68 ohm, Eeff is about 3.23, and delay is about 5.99 ps/mm. The same width reports about 54.83 ohm in the zero-thickness Hammerstad-Jensen comparison, which shows why model spread should be checked before treating a first-pass line width as final.

Accuracy Notes:

Use the calculation for sizing, comparison, and review preparation. Use fabricator modeling or measurement for production sign-off.

• The geometry is single-ended outer-layer microstrip above a reference plane. It does not calculate stripline, coplanar waveguide, differential pairs, or coupled spacing.
• Solder mask is not modeled. A coated outer-layer microstrip can measure differently from a bare trace.
• Laminate Dk depends on material system, resin content, glass style, moisture, temperature, test method, and frequency.
• Extreme W/H ratios, high T/H ratios, and tight impedance tolerances deserve fabricator review or field-solver confirmation.
• Finished copper width can differ from the drawn CAD width because etching and plating shift the manufactured geometry.
• The calculation uses the values entered on the page and does not require a stackup file upload. Copied exports or shared URLs should still be handled as project data if they include sensitive board details.

Advanced Tips:

• Use the board house's finished stackup values when available. Laminate Dk, prepreg thickness, and plated copper can all differ from early layout assumptions.
• Compare the selected model with the alternate model before committing a width. A model spread of several ohms is a reason to ask which equation or field solver the fabricator will use.
• Use Width tolerance with a realistic finished-width tolerance, not just a CAD grid value. A steep sweep curve can turn a small etch shift into a meaningful impedance shift.
• Keep Reference frequency for delay and electrical-length context. It does not make the quasi-static impedance equation frequency dependent.
• For very thin dielectrics, high copper thickness, solder-mask-covered traces, or extreme W/H ratios, treat the number as a first-pass estimate and verify with fabrication data.

Worked Examples:

A common FR-4 starting point uses Dk 4.3, H 0.18 mm, W 0.30 mm, and 35 um copper. With IPC-2141 selected, Characteristic impedance is about 49.68 ohm, Trace over height is W/H 1.667, and Effective dielectric is about 3.23. A 10% width tolerance shifts the modeled impedance from about 53.01 ohm at 0.27 mm to about 46.64 ohm at 0.33 mm.

For a 50 ohm target on that same stackup, Target Z0 mode solves Solved trace width at about 0.2970 mm, or 11.69 mil. The Target comparison row should be near zero because the solver picked the width that lands on the selected model's target.

A thin RF laminate example with Dk 3.48, H 0.10 mm, W 0.20 mm, and 18 um copper produces about 47.68 ohm with IPC-2141 and about 54.08 ohm in the Hammerstad-Jensen comparison. That spread is a cue to confirm the preferred model, copper assumption, and impedance table with the fabricator.

A troubleshooting case is a 150 ohm target on the default 0.18 mm dielectric height and 35 um copper. The target solve cannot reach that impedance with the selected stackup and model, so the validation message appears. Raising dielectric height, lowering Dk, changing the target, or using a different structure is more realistic than forcing an impractically narrow trace.

FAQ:

Glossary:

Z0

Characteristic impedance of the transmission line, reported in ohms.

Dk

Relative permittivity of the laminate material between the trace and reference plane.

Eeff

Effective dielectric constant for the mixed air-and-laminate field around a microstrip.

W/H

Trace width divided by dielectric height, a key geometry ratio for microstrip equations.

T/H

Copper thickness divided by dielectric height, a useful warning ratio on very thin stackups.

TDR

Time-domain reflectometry, a measurement method used to check impedance on a coupon or transmission line.

References:

• IPC-2141A Design Guide for High-Speed Controlled Impedance Circuit Boards table of contents, IPC, March 2004.
• IPC-TM-650 Method 2.5.5.7A, Characteristic Impedance of Lines on Printed Boards by TDR, IPC, March 2004.
• Hammerstad and Jensen, Accurate Models for Microstrip Computer-Aided Design, IEEE MTT-S International Microwave Symposium Digest, 1980.
• Understanding Dielectric Constant for Microwave PCB Materials, Rogers Corporation.