Microstrip Impedance Calculator

Solve direction:

Use the path that matches your stackup question.

Known width Target Z0

Equation model:

Choose the model used for the summary, target solve, and sweep chart.

Substrate preset:

Presets update Dk; use Custom for the board house's exact laminate value.

Dielectric constant:

Use the laminate Dk from your board stackup or material datasheet.

Dielectric height:

Height to the solid reference plane below the trace.

Trace width: {{ widthSliderLabel }}

Enter the finished trace width to estimate the single-ended characteristic impedance.

Target impedance: {{ targetSliderLabel }}

Used as the solve target and as the known-width comparison line.

ohm

Copper thickness:

Use finished copper thickness after plating when you know it.

{{ error }}

Width tolerance:

Preview how much Z0 moves if finished copper width is high or low.

Line length:

Optional route length for delay and electrical-length estimates.

Reference frequency:

Optional frequency for phase length of the entered route.

Sweep span:

Percent of nominal trace width shown on each side in the chart.

Display precision:

Adjust decimals without changing the calculation.

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Check	Value	Detail	Recommendation	Copy
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Microstrip impedance is the characteristic impedance of an outer PCB trace running above a reference plane. It matters when a signal edge or RF wavelength is short enough that the copper trace behaves like a transmission line rather than a simple connection.

A single-ended microstrip is shaped by trace width, dielectric height, copper thickness, and the laminate dielectric constant. Wider copper lowers impedance, a taller dielectric spacing raises it, and a higher Dk usually lowers it because more electric field energy is stored in the board material.

Microstrip cross section with trace width, dielectric height, Dk, and reference plane labels.

Microstrip estimates are useful for choosing a first trace width, checking a board-house stackup, and seeing how much an etch tolerance can move a nominal 50 ohm or 75 ohm line. They do not prove that a finished board will meet a controlled-impedance requirement. Laminate data, solder mask, copper plating, glass weave, nearby copper, launches, vias, bends, and the fabricator's process all affect the measured line.

For controlled production work, the calculated width should become part of a stackup conversation with the PCB fabricator. The final sign-off usually comes from the fabricator's impedance model and, when specified, coupon measurement by time-domain reflectometry.

How to Use This Tool:

Start with the physical stackup, then choose whether you already know the trace width or want the calculator to find a width for a target impedance.

Set Solve direction. Use Known width to estimate Z0 from a finished trace width, or Target Z0 to solve the trace width needed for a selected single-ended impedance.
Choose Equation model. IPC-2141 surface microstrip is the default top-line model and includes copper thickness in its compact equation. Hammerstad-Jensen reference gives a quasi-static zero-thickness comparison.
Enter Dielectric constant and Dielectric height. Use the Dk and trace-to-plane distance from the actual stackup, not just a generic FR-4 guess when the route is impedance-critical.
Enter Trace width in known-width mode, or Target impedance from 5 to 200 ohm in target mode. Common single-ended targets include 50 ohm RF and 75 ohm video, but the correct value comes from the interface or board requirement.
Set Copper thickness from finished copper when available. The IPC-2141 row uses it directly; the Hammerstad-Jensen comparison row reports it for context while using zero-thickness conductor equations.
Open Advanced when fabrication or timing context matters. Width tolerance estimates a low-to-high impedance window, Line length and Reference frequency drive route delay and electrical length, and Sweep span controls the trace-width chart range.
Read Stackup Metrics first, then check Fabrication Window for range warnings, tolerance spread, solder-mask reminders, and fabricator sign-off notes.

If validation appears, fix the named field before using the result. Common causes are zero or negative geometry, Dk outside 1 to 20, target impedance outside 5 to 200 ohm, or a target that the selected stackup and model cannot reach.

Interpreting Results:

The headline result is the selected model's nominal estimate. In known-width mode it is the calculated characteristic impedance. In target mode it is the solved trace width that makes the selected model land on the requested Z0.

How to read microstrip impedance outputs
Output	What to check	Common misread
Characteristic impedance or Solved trace width	Use this as the first-pass nominal value for the selected equation model.	Treating a closed-form estimate as a fabrication guarantee.
Target comparison	Check the signed ohm difference from the target. Near zero means the selected model matches the target.	Ignoring model spread when the two model rows disagree by several ohms.
Trace over height	Review W/H because very narrow or very wide ratios make compact equations less trustworthy.	Assuming the same formula quality across every geometry.
Effective dielectric	Use Eeff for delay and velocity intuition; it should sit between air and the entered Dk.	Reading Eeff as the laminate's actual material Dk.
Width tolerance	Compare the low-to-high impedance range against the impedance tolerance you plan to specify.	Checking only the nominal width when etch tolerance dominates the result.
Model comparison	Use the IPC-2141 and Hammerstad-Jensen pair as a sanity check before sending notes to the fabricator.	Assuming the two formulas should match exactly.

A close target result is still a design estimate. Verify the Dk source, finished copper, solder-mask assumption, reference plane, and tolerance before using the value in controlled-impedance fabrication notes.

Technical Details:

A microstrip line is not fully surrounded by dielectric. Some electric field travels through air above the board, and some travels through laminate below the copper. Effective dielectric constant, Eeff, is a geometry-dependent value that models this mixed field for impedance and delay calculations.

Closed-form microstrip equations estimate quasi-static characteristic impedance from physical dimensions. They are fast and useful during layout, but they simplify real board details. Solder mask, copper roughness, trapezoidal etch shape, weave pattern, dispersion, nearby copper, differential coupling, and connector launches are outside this single-ended bare-microstrip calculation.

Formula Core:

The IPC-2141 surface microstrip equation used for the selected result relates impedance to dielectric constant, dielectric height, finished trace width, and copper thickness.

Z_{0} = \frac{87}{\sqrt{Dk + 1.41}} \ln (\frac{5.98 H}{0.8 W + T})

Here, Z0 is characteristic impedance in ohms, Dk is relative permittivity, H is dielectric height to the reference plane, W is finished trace width, and T is copper thickness. The height, width, and thickness terms must use the same length unit before the equation is evaluated.

Effective dielectric constant for the IPC-style result is estimated from the width-to-height geometry.

E_{eff} = \frac{Dk + 1}{2} + \frac{Dk - 1}{2} \frac{1}{\sqrt{1 + \frac{12 H}{W}}}

The Hammerstad-Jensen comparison uses the normalized width u = W/H. It estimates Eeff with geometry correction terms, then divides an air-line impedance by the square root of Eeff. In this tool that comparison is a zero-thickness reference, so it may differ from the IPC-2141 row when copper thickness is large relative to dielectric height.

Z_{0} = \frac{60 \ln (\frac{f (u)}{u} + \sqrt{1 + {(\frac{2}{u})}^{2}})}{\sqrt{E_{eff}}}

Microstrip calculator input and validation bounds
Input or setting	Accepted values	Effect on the result
Dielectric constant	1 to 20	Higher Dk generally lowers impedance and increases delay.
Dielectric height	Greater than 0, in mm, mil, um, or inch	Larger H raises impedance for the same trace width.
Trace width	Greater than 0, in mm, mil, um, or inch	Larger W lowers impedance and raises the W/H ratio.
Target impedance	5 to 200 ohm	Target mode searches for the width that reaches this Z0 on the selected stackup.
Copper thickness	0 or greater, in um, mil, oz copper, or mm	IPC-2141 includes T directly; the Hammerstad-Jensen comparison shown here does not.
Width tolerance	0 or greater, as percent, mm, mil, or um	Creates the low-width and high-width impedance estimates in Fabrication Window.
Sweep span	10% to 90%	Controls how far the trace-width chart sweeps around the nominal or solved width.

Propagation delay uses Eeff to estimate velocity factor. A larger Eeff slows the signal because the wave spends more effective time in dielectric material.

delay per mm = \frac{\sqrt{E_{eff}}}{c} 10^{9}

For example, Dk 4.3, H 0.18 mm, W 0.30 mm, and 35 um copper produce about 49.68 ohm with the IPC-2141 selection, Eeff about 3.23, and about 5.99 ps/mm delay. The same nominal geometry reports about 54.83 ohm in the zero-thickness Hammerstad-Jensen comparison, which is a useful reminder that equation choice and copper assumptions can move a first-pass result by several ohms.

Accuracy Notes:

Use the calculation for sizing and comparison, not final production proof.

The model is for single-ended microstrip above a reference plane. It does not calculate differential pairs, stripline, coplanar waveguide, or coupled-line spacing.
Outer-layer solder mask is reported as not modeled. A coated microstrip can measure differently from a bare microstrip.
Dk is not a universal FR-4 constant. It depends on laminate system, resin content, glass style, moisture, temperature, test method, and frequency.
Very small or very large W/H ratios, high T/H ratios, and tight impedance tolerances deserve fabricator review or a field solver.
Finished copper width is often different from drawn copper width because etching and plating shift the manufactured geometry.

Worked Examples:

A common outer-layer FR-4 starting point uses Dk 4.3, H 0.18 mm, W 0.30 mm, and 35 um copper. With the IPC-2141 model selected, Characteristic impedance is about 49.68 ohm, Trace over height is W/H 1.667, and Effective dielectric is about 3.23. The Width tolerance window at 10% spans roughly 53.01 ohm at 0.27 mm to 46.64 ohm at 0.33 mm.

For a 50 ohm target on that same stackup, Target Z0 mode solves Solved trace width at about 0.2970 mm, or 11.69 mil. The Target comparison row should be near zero because the solver picked the width that lands on the selected model's target.

For a thin RF laminate example, Dk 3.48, H 0.10 mm, W 0.20 mm, and 18 um copper produce about 47.68 ohm with the IPC-2141 selection and about 54.08 ohm in the Hammerstad-Jensen comparison. That spread is a prompt to check model choice, copper assumptions, and the fabricator's preferred impedance table before treating either number as final.

A troubleshooting case is a 150 ohm target on the default 0.18 mm dielectric height and 35 um copper. The tool reports that the target is outside the solvable width range for that stackup and model. Raise the dielectric height, lower the Dk, change the impedance target, or ask the fabricator whether that geometry is practical before forcing a very narrow trace.

FAQ:

Why does a wider trace lower impedance?

A wider trace has more capacitance to the reference plane. Higher capacitance lowers characteristic impedance when the dielectric height and material stay the same.

Should I use IPC-2141 or Hammerstad-Jensen?

Use the model your team or fabricator expects for the first pass, then compare the other row. IPC-2141 includes copper thickness in the selected equation, while the Hammerstad-Jensen comparison shown here is a zero-thickness reference.

Why does the result warn about W/H?

The Fabrication Window flags W/H outside roughly 0.1 to 3.0 because compact microstrip equations are less reliable for extreme geometries. That warning does not mean the board cannot be built; it means the estimate needs better verification.

Does the reference frequency change the impedance?

No. The reference frequency is used for Route delay and electrical-length reporting. The quasi-static impedance equations do not become a frequency-dependent electromagnetic solver.

What should I do if target width solve fails?

The target is outside the width range that the selected stackup and model can reach. Change dielectric height, Dk, copper thickness, target impedance, or model, then confirm the geometry with the fabricator.

Are my stackup values uploaded anywhere?

The calculation uses the values entered on the page and does not require a file upload or account lookup. Treat shared URLs or copied exports as ordinary project data if they include sensitive stackup details.

Glossary:

Z0: Characteristic impedance of the transmission line, reported in ohms.
Dk: Relative permittivity of the dielectric material used between the trace and reference plane.
Eeff: Effective dielectric constant for the mixed air-and-laminate field around a microstrip.
W/H: Trace width divided by dielectric height, a key geometry ratio for microstrip equations.
T/H: Copper thickness divided by dielectric height, used to judge when copper thickness is large relative to the stackup.
TDR: Time-domain reflectometry, a measurement method used to check impedance on a test coupon or transmission line.

References:

IPC-2141A Design Guide for High-Speed Controlled Impedance Circuit Boards table of contents, IPC, March 2004.
IPC-TM-650 Method 2.5.5.7A, Characteristic Impedance of Lines on Printed Boards by TDR, IPC, March 2004.
Microstrip Transmission Lines, Engineering LibreTexts.
Managing PCB Materials: Dielectric Constant (Dk), Rogers Corporation, September 11, 2018.
Microstrip and Stripline Transmission Lines, Polar Instruments.