Compute Throughput Calculator
Estimate theoretical FLOP/s or OP/s from architecture inputs, then compare compute utilization with the memory-bandwidth roof.{{ summaryTitle }}
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Limiting roof
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Interpretation limit
This is a roofline ceiling, not a benchmark or a guarantee. Validate the operation-count convention, sustained clock, memory level, and measured workload behavior with an appropriate profiler.
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A processor's advertised arithmetic rate is a ceiling, not the speed every workload will reach. The ceiling combines how many processing groups can issue work, how many lanes or cores participate, how many operations each lane can issue per cycle, and the clock sustained during that work.
Data movement creates a second ceiling. A kernel that performs little arithmetic for each byte transferred may run out of memory bandwidth long before it uses all available arithmetic units. A kernel that reuses data heavily can move beyond that bandwidth-limited region and become compute-bound.
- Compute peak
- The architecture arithmetic ceiling at the declared precision, issue rate, operation-count convention, and sustained clock.
- Arithmetic intensity
- Operations performed per byte transferred at the same memory level used for the bandwidth figure.
- Memory roof
- Sustainable bandwidth multiplied by arithmetic intensity, expressed as operations per second.
- Ridge intensity
- The operations-per-byte value where the memory roof reaches the compute peak.
Precision and counting conventions must be consistent. Floating-point multiply-add (FMA) is commonly counted as two floating-point operations, one multiply and one add. If a published operations-per-cycle figure already includes both, applying another factor of two overstates throughput.
A roofline estimate helps check specifications, compare architectural assumptions, and identify the lower theoretical limit. It does not measure a running kernel. Instruction mix, occupancy, dependencies, cache behavior, memory access patterns, thermal limits, and software efficiency can all keep observed throughput below the calculated roof.
How to Use This Tool:
Describe one precision path and one matching memory level so the compute and bandwidth assumptions are comparable.
- Choose Precision. Floating-point selections report FLOP/s; INT8 reports OP/s.
- Select the FMA convention. Use two operations only when the entered base issue rate does not already count both the multiply and add.
- Enter the number of Compute units, lanes or cores per unit, base operations per cycle per lane, and the relevant sustained clock. Use values for the same precision and execution path.
- Enter sustainable memory bandwidth and arithmetic intensity for the same memory boundary. Mixing DRAM bandwidth with L1 traffic intensity produces a roof with no coherent physical meaning.
- Set a low and high compute-utilization percentage. Read the attainable range with the limiting roof; low utilization cannot exceed high utilization.
Interpreting Results:
Theoretical compute peak answers how much arithmetic the declared path could issue. Memory roof answers how much arithmetic the declared data rate can feed at the selected intensity. The lower value is the relevant ceiling before the utilization range is applied.
- Memory-bound means bandwidth multiplied by intensity is below compute peak. More arithmetic throughput alone cannot lift that roof.
- Compute-bound means the memory roof is above compute peak. The declared issue rate is the lower ceiling.
- Attainable ceiling clips the utilization-adjusted compute range at the memory roof. A narrow or flat result can show where bandwidth cuts through the selected range.
- Ridge intensity is a break-even point, not a measured property of the workload. Compare it with intensity obtained from profiling at the same memory level.
Do not compare the result with benchmark output until precision, operation counting, clock basis, bandwidth level, and workload operation definition all match. FLOP/s and integer OP/s are not interchangeable measures.
Technical Details:
The classic roofline model takes the minimum of a flat compute ceiling and a bandwidth ceiling that rises with arithmetic intensity. This calculation adds an explicit utilization interval, then clips each endpoint against the same memory roof.
Formula Core:
Clock and memory bandwidth use decimal giga, so each entered GHz or GB/s contributes a factor of 109. The FMA factor f is 2 when multiply and add are counted separately and 1 when the base issue rate already counts them.
| Symbol | Meaning | Unit |
|---|---|---|
| U | Compute units | Count |
| L | Lanes or cores per unit | Count per unit |
| O | Base operations per cycle per lane | Operation/cycle/lane |
| c | Sustained clock | GHz |
| B | Sustainable memory bandwidth | GB/s |
| I | Arithmetic intensity | Operation/byte |
| u | Low or high utilization endpoint | Percent |
With 80 compute units, 64 lanes each, one base operation per cycle, an FMA factor of 2, and a 1.5 GHz clock, compute peak is 15.36 TFLOP/s. At 1,000 GB/s and 10 FLOP/B, the memory roof is 10 TFLOP/s. A 60% to 85% utilization interval produces 9.216 to 13.056 TFLOP/s before clipping and 9.216 to 10 TFLOP/s after the memory roof is applied.
Rule Core:
| Condition | Classification |
|---|---|
| Memory roof < compute peak | Memory-bound theoretical roof |
| Memory roof = compute peak | Balanced at the ridge point |
| Memory roof > compute peak | Compute-bound theoretical roof |
| Memory roof >= high utilized compute | Compute limits the full utilization interval |
| Low utilized compute < memory roof < high utilized compute | Memory roof crosses the interval |
| Memory roof <= low utilized compute | Memory limits the full interval |
Rates remain unrounded through the comparisons and are formatted with decimal M, G, T, or P prefixes for display. The calculation is deterministic and contains no device lookup or benchmark measurement.
References:
- Roofline: An Insightful Visual Performance Model for Multicore Architectures, University of California, Berkeley, October 17, 2008.
- Nsight Compute Profiling Guide: Roofline Charts, NVIDIA.
- NIST Guide to the SI, Chapter 4, National Institute of Standards and Technology.