Timing Diagram Generator

WaveJSON source:

Declare up to 24 signal lanes and 80 time slots per lane. This renders the declaration; it does not simulate hardware.

Order lane review by longest span:

Off is neutral and keeps source order. Turn it on to sort the chart and ledger by declared time slots without changing the SVG.

The chart renderer is unavailable. Exact lane spans remain available in Signal ledger.

Signal	Group	Wave	Slots	States	Data labels	Copy
{{ row.name }}	{{ row.group \|\| '—' }}	`{{ row.wave }}`	{{ row.slots }}	{{ row.states }}	{{ row.data \|\| '—' }}

Digital signals are easier to review when their changes share one horizontal time axis. A timing diagram lines up clocks, control lines, buses, and event relationships so a reader can see which state came first, how long it lasted, and which transitions were meant to coincide.

The drawing is a declaration of expected or observed behavior, not a hardware simulation. It does not calculate propagation delay, setup time, hold time, metastability, or electrical voltage. Those facts must come from a device specification, simulator, logic analyzer, or oscilloscope.

Signal lane: One named row whose wave string describes states or clock activity over successive time slots.
Data label: Text attached to a bus-shaped state, such as an address, command, or transaction phase.
Node and edge: A named point on a lane and a relationship drawn between two named points.

Periods and phases change how a lane is positioned against the shared axis. Groups organize related lanes, while ticks and tocks add time labels above or below the drawing. These choices improve communication only when everyone reading the diagram uses the same time basis.

A clean rendering can still describe the wrong transaction. Compare lane names, data labels, transition order, and relationship arrows with the reviewed protocol or trace before treating the diagram as evidence.

How to Use This Tool:

Write a bounded WaveJSON object that describes the lanes and relationships you need to review.

Enter strict JSON in WaveJSON source. Start with a non-empty signal array and give every material lane a name and wave.
Add data labels for bus states, node markers for named points, and an edge array only when those relationships are part of the reviewed behavior.
Use head, foot, or config.hscale for time labels and horizontal scale. Correct the first validation message if the JSON, property set, wave symbols, or limits are rejected.
Enable Order lane review by longest span only when duration comparison matters. It reorders the lane chart and ledger while leaving the rendered SVG in source order.
Compare the timing diagram with Lane spans and Signal ledger. Check the maximum slot count, clock count, lane order, state count, and data labels before saving the drawing.

Interpreting Results:

The SVG is the visual reading of the accepted WaveJSON. The maximum time-slot figure is the longest declared lane, not elapsed time in seconds. A clock count reports lanes containing clock symbols; it does not measure frequency.

Use lane state counts to spot dense activity, not to infer switching power or bus utilization.
Treat edges as annotated relationships between declared nodes, not measured causal or timing guarantees.
Verify important boundaries against the source order and the underlying specification or trace.

Technical Details:

WaveJSON represents each lane as a compact sequence of symbols. Most symbols consume one time slot; a period marker extends the previous state, while visual gap and phase markers do not increase the reported slot count. The accepted object is normalized before it is rendered, so unsupported properties never reach the diagram.

Rule Core:

Accepted timing diagram source rules
Area	Accepted rule	Boundary
Root	Strict JSON object with `signal` and optional `edge`, `head`, `foot`, and `config`	20,000 source characters
Lanes	`name` and `wave`, with optional `data`, `node`, `period`, and `phase`	1 to 24 lanes; 80 slots per lane
Wave string	Clock symbols `pPnNhHlL`, states `01xduz=23456789`, extension `.`, and markers `\|<>`	The first counted symbol cannot be `.`
Groups	A group is an array beginning with its name followed by lanes or child groups	At most 2 nested group levels
Data	Text or an array of text, finite numbers, and booleans	80 labels per lane; 80 characters per array label
Relationships	Node markers use letters, numbers, and `.`; edges are WaveDrom relationship strings	32 edges; 120 characters per edge
Lane timing	`period` from 0.25 to 16 and `phase` from -80 to 80	Both endpoints are accepted
Scale and labels	`config.hscale` is 1 to 4; `head` and `foot` accept text, tick, tock, and every	`every` is an integer from 1 to 80

Transformation Core:

Timing diagram transformation stages
Stage	Transformation	Result
Parse	Read strict JSON and reject a non-object root.	One bounded WaveJSON object
Validate	Allow only the documented root, lane, header, and scale properties; clean visible control characters from labels.	Renderable text and known properties only
Measure	Walk groups and lanes, count slots, state changes, clock-bearing lanes, groups, and edges.	Lane spans and signal ledger values
Render	Pass the normalized declaration to WaveDrom 3.6.2.	An SVG timing diagram

Sorting uses descending declared slot count with original order as the tie-breaker. It affects review rows and the duration chart only; the normalized diagram declaration and SVG retain source order.

FAQ:

Why does valid WaveDrom source fail to load?

The accepted profile is intentionally smaller than the full WaveDrom language and requires strict JSON. Remove unsupported properties, use double-quoted JSON keys and strings, and stay within the lane, slot, group, label, and edge limits.

Does the diagram prove that a circuit meets timing?

No. It renders the declared sequence. Verify real timing with the relevant device limits, simulation, static timing analysis, or captured measurements.

References:

Hitchhiker's Guide to the WaveDrom, WaveDrom.